Design for testability using register-transfer level partial scan selection

Author

Motohara, Akira ; Takeoka, Sadami ; Hosokawa, Toshinori ; Ohta, Mitsuyasu ; Takai, Yuji ; Matsumoto, Michihiro ; Muraoka, Michiaki

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

209

Lastpage

215

Abstract

An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented

Keywords

VLSI; design for testability; finite state machines; integrated circuit design; integrated circuit testing; logic CAD; logic gates; logic testing; CAD; RTL design; VLSI design; control circuits; data path circuits; design for testability; experimental results; gate level ATPG; partial scan selection; register-transfer level design; registers; state machines; testability analysis; top down design; Automatic test pattern generation; Built-in self-test; Central Processing Unit; Circuit synthesis; Circuit testing; Costs; Design for testability; Logic testing; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486225

Filename

486225