BIST with negligible aliasing through random cover circuits

Author

Bogue, T. ; Jürgensen, H. ; Gössel, M.

Author_Institution

Univ. of Western Ontario, London, Ont., Canada

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

223

Lastpage

228

Abstract

In this paper, a new modified BIST structure is investigated. The output of the MISA is monitored during the test by an error detection circuit which is composed of two simple cover circuits. To simplify the cover construction, the cover circuits are randomly chosen to be active for some of the outputs of the MISA. Thus, a time-consuming fault simulation can be completely avoided. The overhead for the cover circuits is determined for several of the ISCAS´85 and Berkeley benchmark circuits. These simulation experiments show that a significant reduction of the aliasing probability can be achieved, confirming and far surpassing theoretically predicted improvements. Moreover, this improvement can be achieved at a nearly negligible cost in additional hardware

Keywords

built-in self test; circuit analysis computing; fault diagnosis; logic CAD; logic testing; performance evaluation; probability; BIST; MISA; aliasing probability; benchmark circuits; built in self test; circuit testing; cost; error detection circuit; logic circuit; negligible aliasing; random cover circuits; simple cover circuits; simulation experiments; time-consuming fault simulation; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Costs; Electrical fault detection; Fault detection; Hardware; Monitoring; Predictive models;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486227

Filename

486227