DocumentCode
3247297
Title
Architecture of AVS hardware decoding system
Author
Peng, Cong ; Huang, Chao ; Wang, Ronggang ; Dai, Jianwei ; Zhao, Yangshen
Author_Institution
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China
fYear
2004
fDate
20-22 Oct. 2004
Firstpage
306
Lastpage
309
Abstract
This paper introduces the architecture of an AVS (audio video coding standard working group of China) hardware decoding system. The system includes system layer decoding, video decoding and audio decoding. It supports 720p/1080i HD (high-definition) format real-time decoding. A VLSI chip is designed by using this architecture.
Keywords
VLSI; audio coding; decoding; video coding; AVS hardware decoding system; VLSI chip; audio decoding; audio video coding standard; high-definition format real-time decoding; system layer decoding; video decoding; Control systems; Decoding; Displays; Frequency; Hardware; High definition video; Memory architecture; Streaming media; Very large scale integration; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Multimedia, Video and Speech Processing, 2004. Proceedings of 2004 International Symposium on
Print_ISBN
0-7803-8687-6
Type
conf
DOI
10.1109/ISIMP.2004.1434061
Filename
1434061
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