Yield improvement in dense EEPROM by bit mapping and experimental design

This paper demonstrates how combined activities of bit mapping of dense EEPROM array, layout overlay, and failure analysis can lead to experimental design to improve yield. In this methodology a complicated detection of failing bits in a large array is transformed to multi variable design with simple detection. Specifically, it describes the process of detection of word line failures caused by salicide voids and how a simple test chip and experimental design can bring this problem to resolution.