Title :
Performance driven multiple-source bus synthesis using buffer insertion
Author :
Tsai, Chia-Chun ; Kao, De-Yu ; Cheng, Chung-Kuan ; Lin, Ting-Ting
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fDate :
29 Aug-1 Sep 1995
Abstract :
A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively
Keywords :
VLSI; buffer circuits; circuit CAD; heuristic programming; integrated circuit design; VLSI systems design; buffer insertion; delay minimisation; heuristic algorithm; multiple sink bus; performance driven multiple source bus synthesis; signal delay time; Capacitance; Computer science; Delay effects; Driver circuits; Heuristic algorithms; Routing; Timing; Topology; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
DOI :
10.1109/ASPDAC.1995.486234
