Title :
Optimum PLA folding through boolean satisfiability
Author :
Quintana, J.M. ; Avedillo, M.J. ; Parra, M.P. ; Huertas, J.L.
Author_Institution :
Centro Nacional de Microelectron., Sevilla, Spain
fDate :
29 Aug-1 Sep 1995
Abstract :
This paper proposes an algorithm for optimum PLA folding based on its formulation as a problem of boolean satisfiability. A logical expression is derived such that the assignment of variables that satisfies it defines a folding with a minimum number of columns. The proposed algorithm uses BDDs to represent boolean functions and incorporates novel reduction techniques, obtaining satisfactory results
Keywords :
Boolean functions; computability; minimisation of switching nets; programmable logic arrays; BDDs; PLA folding; boolean functions; boolean satisfiability; logical expression; reduction techniques; Binary decision diagrams; Boolean functions; Data structures; Integrated circuit synthesis; Logic arrays; Logic design; Logic functions; Logic gates; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
DOI :
10.1109/ASPDAC.1995.486236
