• DocumentCode
    3247686
  • Title

    Manipulation of regular expressions under length constraints using zero-suppressed-BDDs

  • Author

    Ishihara, Shinya ; Minato, Shin-ichi

  • Author_Institution
    Adv. LSI Lab., NTT LSI Labs., Kanagawa, Japan
  • fYear
    1995
  • fDate
    29 Aug-1 Sep 1995
  • Firstpage
    391
  • Lastpage
    396
  • Abstract
    We present a new technique that broadens the scope of BDD application. It is a method for manipulating regular expressions that represent sets of sequences including repetitions of symbols. In general, sequences in the set represented by a regular expression have an infinite length and this makes representing and manipulating them difficult. In this paper, we introduce length constraints into a representation of regular expressions. Under these constraints, our method can represent and manipulate large-scale sets of sequences of regular expressions compactly and uniquely and greatly accelerates operations of regular expressions. As regular expressions can represent behaviors of a finite state machine, our technique provides a useful analysis method of finite state machines and can be applied to formal hardware verification techniques
  • Keywords
    decision tables; finite state machines; formal verification; logic design; logic testing; BDDs; finite state machines; formal hardware verification; length constraints; regular expressions; sequences; Acceleration; Automata; Binary decision diagrams; Boolean functions; Design methodology; Hardware; Laboratories; Large scale integration; Large-scale systems; Logic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
  • Conference_Location
    Chiba
  • Print_ISBN
    4-930813-67-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1995.486250
  • Filename
    486250