A cycle-efficient sample-parallel EBCOT architecture for JPEG2000 encoder

Author

Xing, Zhao ; Ye, Yang ; Xing, Qin ; Wu Tuo ; Hai-Bin, Shen

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China

fYear

2004

fDate

20-22 Oct. 2004

Firstpage

386

Lastpage

389

Abstract

In this paper, a novel cycle-efficient sample-parallel architecture for an EBCOT entropy encoder, used in JPEG2000, is proposed. The architecture consists of a pass-parallel context modeling unit capable of simultaneous processing of four samples, and a pipelined binary arithmetic coder running at double the system clock rate to match the processing rate of the context modeling unit. Simulation results show that this design reduces processing time by more than 50% to 60% compared with previous pass-parallel architectures, and is able is process a 512×512 grayscale image in approximately 0.005 second at 100 MHz system clock rate.

Keywords

binary codes; block codes; entropy codes; image coding; pipeline arithmetic; 0.005 s; 100 MHz; 262144 pixel; 512 pixel; EBCOT entropy encoder; JPEG2000 encoder; computational complexity; cycle-efficient EBCOT; embedded block coding with optimized truncation algorithm; entropy coding; grayscale image; pass-parallel context modeling unit; pipelined MQ coder; pipelined binary arithmetic coder; processing rate; processing time reduction; sample-parallel EBCOT architecture; still image compression standard; system clock rate; Acceleration; Arithmetic; Clocks; Context modeling; Gray-scale; Hardware; Image coding; Parallel processing; Process design; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Multimedia, Video and Speech Processing, 2004. Proceedings of 2004 International Symposium on

Print_ISBN

0-7803-8687-6

Type

conf

DOI

10.1109/ISIMP.2004.1434081

Filename

1434081