• DocumentCode
    3247820
  • Title

    Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends

  • Author

    Anders, M. ; Krishnamurthy, R. ; Spotten, R. ; Soumyanath, K.

  • Author_Institution
    Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
  • fYear
    2001
  • fDate
    14-16 June 2001
  • Firstpage
    23
  • Lastpage
    24
  • Abstract
    We present an accurate (to within 3%, across two process generations), three parameter, closed form, time-domain technique for evaluating the noise response of domino circuits. We evaluate the robustness of scaled topologies to show that conventional domino circuits will cease to be useful around the 70 nm generation. The paper concludes with possible device/circuit approaches to extend domino circuit usefulness.
  • Keywords
    MOS logic circuits; circuit simulation; integrated circuit noise; logic simulation; time-domain analysis; 70 nm; MOS logic; closed form technique; domino circuits; dynamic circuits; noise response; process generations; robustness; scaled topologies; scaling trends; time-domain technique; Circuit analysis; Circuit noise; Delay; MOS devices; Noise reduction; Noise robustness; Pulse width modulation inverters; Space vector pulse width modulation; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    4-89114-014-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2001.934181
  • Filename
    934181