A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates

Author

Alvandpour, A. ; Krishnamurthy, R. ; Soumyanath, K. ; Borkar, S.

Author_Institution

Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

14-16 June 2001

Firstpage

29

Lastpage

30

Abstract

Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.

Keywords

VLSI; integrated circuit design; integrated logic circuits; leakage currents; logic gates; 0.13 micron; 8 to 32 bit; VLSI; conditional keeper technique; dynamic gates; dynamic output; evaluation phase; leakage currents; leaky gates; robustness; Circuit simulation; Circuit topology; Clocks; Delay; Energy consumption; Leakage current; Microprocessors; Noise level; Noise robustness; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934184

Filename

934184