Title :
A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]
Author :
Okuda, Y. ; Horiguchi, M. ; Nakagome, Y.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A DLL circuit featuring variable "lock mode" and correction of duty-cycle error is described. The DLL circuit has a wide locking range from under 66 MHz to 400 MHz. The chip area and power consumption at 400 MHz are 0.33 mm/sup 2/ and 24 mW, respectively.
Keywords :
DRAM chips; delay lock loops; error correction; 24 mW; 66 to 400 MHz; SDRAMs; adaptive-lock-mode DLL circuit; chip area; duty-cycle error correction; locking range; power consumption; Circuits; Clocks; Computer errors; Delay effects; Differential amplifiers; Energy consumption; Error correction; Frequency; Laser mode locking; Voltage;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934188
