A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

Author

Yido Koo ; Hyungki Huh ; Yongsik Cho ; Jeongwoo Lee ; Joonbae Park ; Kyeongho Lee ; Deog-Kyoon Jeong ; Wonchan Kim

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea

fYear

2001

fDate

14-16 June 2001

Firstpage

43

Lastpage

46

Abstract

This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; cellular radio; circuit tuning; code division multiple access; frequency synthesizers; integrated circuit noise; low-power electronics; personal communication networks; phase noise; 0.35 micron; 3.0 V; 60 mW; CDMA wireless systems; CMOS frequency synthesizer; PCS; cellular radio; channel spacing; charge-averaging charge pump; coarse tuning; dual-path loop filter; phase noise characteristics; power dissipation; time constant; CMOS technology; Channel spacing; Charge pumps; Circuit optimization; Filters; Frequency synthesizers; Phase noise; Power dissipation; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934190

Filename

934190