Automatic calibration of modulated /spl Sigma/-/spl Delta/ frequency synthesizers

Author

McMahill, D.R. ; Sodini, C.G.

Author_Institution

MIT, Cambridge, MA, USA

fYear

2001

fDate

14-16 June 2001

Firstpage

51

Lastpage

54

Abstract

This paper describes a sigma-delta (/spl Sigma/-/spl Delta/) synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an in-service automatic calibration circuit which tunes the phase locked loop (PLL) to compensate for process tolerance and temperature variation. The PLL, including 1.8 GHz voltage controlled oscillator (VCO), /spl Sigma/-/spl Delta/ modulator, and calibration circuit has been implemented in a 0.6 micron BiCMOS integrated circuit. The test chip achieves 2.5 Mbit/second using GFSK and 5.0 Mbit/second using 4-FSK.

Keywords

BiCMOS integrated circuits; calibration; frequency shift keying; frequency synthesizers; minimum shift keying; phase locked loops; sigma-delta modulation; voltage-controlled oscillators; 0.6 micron; 1.8 GHz; 2.5 Mbit/s; 5.0 Mbit/s; BiCMOS integrated circuit; GFSK/GMSK; Gaussian frequency modulation; calibration circuit; in-service automatic calibration circuit; minimum shift keying; modulated /spl Sigma/-/spl Delta/ frequency synthesizers; phase locked loop; process tolerance; temperature variation; voltage controlled oscillator; Calibration; Delta-sigma modulation; Frequency modulation; Frequency shift keying; Frequency synthesizers; Phase locked loops; Technological innovation; Temperature; Tuned circuits; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934192

Filename

934192