Title :
A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip
Author :
Ramchan Woo ; Chi-Weon Yoon ; Jeonghoon Kook ; Se-Joong Lee ; Kangmin Lee ; Yong-Ha Park ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.
Keywords :
computer graphic equipment; digital signal processing chips; embedded systems; low-power electronics; mobile computing; multimedia computing; notebook computers; rendering (computer graphics); 0.18 micron; 120 mW; 3.2 GB/s; 6 Mbit; CMOS embedded memory logic technology; E3GRE; area consumption; embedded 3D graphics rendering engine; line-block mapping; logically local frame-buffer; mobile PDA-chip; polygon-dependent access; power consumption; read-modify-write data transaction; run-time reconfigurable bus; runtime reconfigurable bus; CMOS logic circuits; Energy consumption; Engines; Graphics; Laboratories; Random access memory; Reconfigurable logic; Rendering (computer graphics); Runtime; Simultaneous localization and mapping;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934206