Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications

Author

Chi-Weon Yoon ; Jeonghoon Kook ; Ramchan Woo ; Se-Joong Lee ; Kangmin Lee ; Hoi-Jun Yoo

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

2001

fDate

14-16 June 2001

Firstpage

99

Lastpage

102

Abstract

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.

Keywords

data compression; industrial property; large scale integration; low-power electronics; mobile computing; motion compensation; multimedia computing; random-access storage; video codecs; 0.18 micron; 1.25 Mbit; 16.3 mW; 20 MHz; DRAM frame buffer; EML technology; adaptive fetch control; block IP; data buffer; datapath switching; distributed nine-tiled mapping; embedded DRAM macro; frame buffer; low power electronics; motion compensation; partial activation scheme; portable multimedia applications; Circuits; Computer buffers; Decoding; Energy consumption; Frequency; MPEG 4 Standard; Motion compensation; Multimedia systems; Random access memory; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934207

Filename

934207