Title :
A 1 GHz power efficient single chip multiprocessor system for broadband networking applications
Author :
Santhanam, S. ; Allmon, R. ; Anne, K. ; Blake, R. ; Bunger, N. ; Campbell, B. ; Carlson, M. ; Zongjian Chen ; Cheng, J. ; Tuan Do ; Dobberpuhl, D. ; Ingino, J. ; Kidd, D. ; Kruckemyer, D. ; Jong Lee ; Murray, D. ; Nishimoto, S. ; O´Donnell, L. ; Oykher, M
Author_Institution :
Broadcom Corp., San Jose, CA, USA
Abstract :
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD´s Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; microprocessor chips; parallel architectures; pipeline processing; system buses; 0.15 micron; 1 GHz; 1.2 V; 13 W; 512 KB; 66 MHz; Broadcom BCM12500; CMOS technology; DDR memory controller; Gigabit Ethernet MAC; L2 cache; Lightning Data Transport; PCI bus; SOC; ZBbus; broadband networking applications; network centric tasks; power dissipation; single chip multiprocessor system; split transaction fully coherent multi processor bus; Bandwidth; CMOS technology; Delay; Ethernet networks; Lightning; Multiprocessing systems; Pipelines; Power dissipation; Protection; System-on-a-chip;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934209
