• DocumentCode
    3248448
  • Title

    Description and verification of RTL designs using multiway decision graphs

  • Author

    Zhou, Zijian ; Song, Xiaoyu ; Corella, Francisco ; Cerny, Eduard ; Langevin, Michel

  • Author_Institution
    Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
  • fYear
    1995
  • fDate
    29 Aug-1 Sep 1995
  • Firstpage
    575
  • Lastpage
    580
  • Abstract
    Traditional OBDD-based methods of automated verification suffer from, the drawback that they require a binary representation of the circuit. Multiway Decision Graphs (MDGs) combine the advantages of OBDD techniques with those of abstract types. RTL designs can be compactly described by MDGs using abstract data values and uninterpreted function symbols. We have developed MDG-based techniques for combinational verification, reachability analysis, verification of behavioral equivalence, and verification of a microprocessor against its instruction set architecture. We report on the results of several verification experiments using our MDG package
  • Keywords
    abstract data types; formal specification; formal verification; logic testing; reachability analysis; OBDD; RTL designs; abstract types; automated verification; behavioral equivalence; combinational verification; multiway decision graphs; reachability analysis; Feedback circuits; Hardware; Microprocessors; Packaging; Partitioning algorithms; Reachability analysis; Registers; Space exploration; State-space methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
  • Conference_Location
    Chiba
  • Print_ISBN
    4-930813-67-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1995.486372
  • Filename
    486372