Title :
Sub-1 V process-compensated MOS current generation without voltage reference
Author :
Narendra, S. ; Klowden, D. ; De, V.
Author_Institution :
Microprocessor Res. Lab., Intel Corp., Hillsboro, OR, USA
Abstract :
A sub-1 V process-compensated MOS current generation concept that does not require a reference voltage is presented. A theoretical model for the concept showing reduced sensitivity to variation in process parameters including gate oxide thickness and threshold voltage is derived. MOSFET device measurements and circuit simulation results show reduced process sensitivity and low voltage operation.
Keywords :
MOS integrated circuits; VLSI; circuit simulation; low-power electronics; reference circuits; MOSFET device measurements; circuit simulation results; gate oxide thickness; low voltage operation; process parameters; process sensitivity; process-compensated MOS current reference generation; threshold voltage; CMOS technology; Costs; DC generators; Equations; MOSFET circuits; Microprocessors; Photonic band gap; Resistors; Temperature; Threshold voltage;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934221
