Novel VLSI implementation for triplet-based spike-timing dependent plasticity

Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to play an important role in learning and memory in the brain. In conventional pair-based STDP learning, synaptic weights are altered by utilizing the temporal difference between pairs of pre- and post-synaptic spikes. This learning rule, however, fails to reproduce reported experimental measurements when using stimuli either by patterns consisting of triplet or quadruplet of spikes or increasing the repetition frequency of pairs of spikes. Significantly, a previously described spike triplet-based STDP rule succeeds in reproducing all of these experimental observations. In this paper, we present a new spike triplet-based VLSI implementation, that is based on a previous pair-based STDP circuit [1]. This implementation can reproduce similar results to those observed in various physiological STDP experiments, in contrast to traditional pair-based VLSI implementation. Simulation results using standard 0.35 μm CMOS process of the new circuit are presented and compared to published experimental data [2].