DocumentCode
3248910
Title
P-boosted source followers: a robust energy-efficient bus driver technique
Author
Krishnamurthy, R. ; Soumyanath, K. ; Ayers, D.
Author_Institution
Microprocessor Res. Lab., Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
14-16 June 2001
Firstpage
191
Lastpage
192
Abstract
This paper describes a PMOS-boosted source follower bus driver technique for robust, full-swing, on-chip buses. A 10% performance improvement on a 128-bit L1 cache bus is achieved on a 0.18 /spl mu/m production 64-bit processor. A regional clock grid driver scheme with 14% energy reduction is also described.
Keywords
CMOS digital integrated circuits; driver circuits; high-speed integrated circuits; low-power electronics; microprocessor chips; 0.18 micron; 128 bit; 64 bit; L1 cache bus; PMOS-boosted source follower; energy reduction; energy-efficient bus driver technique; full-swing onchip buses; regional clock grid driver scheme; robust bus driver technique; CMOS technology; Clocks; Delay effects; Driver circuits; Energy efficiency; Inverters; MOS devices; Noise robustness; Production; Repeaters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934234
Filename
934234
Link To Document