Title :
A 6.25 ns random access 0.25 /spl mu/m embedded DRAM
Author :
DeMone, P. ; Dunn, M. ; Haerle, D. ; Jin-Ki Kim ; Macdonald, D. ; Nyasulu, P. ; Perry, D. ; Smith, S. ; Wojcicki, T. ; Zhouhong Zhang
Author_Institution :
MOSAID Technol. Inc., Kanata, Ont., Canada
Abstract :
A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.
Keywords :
DRAM chips; embedded systems; memory architecture; 0.25 micron; 6.25 ns; circuit design; control architecture; cycle time; embedded DRAM; hard macro; latency; random access operation; stacked capacitor blended logic process; Capacitors; Circuit synthesis; Computational modeling; Computer architecture; Computer networks; Delay; Embedded computing; Logic; Random access memory; Signal processing;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934251
