A compact lateral-SOI BJT model for RF circuit simulation

Author

Fuse, Tsuneaki ; Kawanaka, Shigeru ; Inoh, Kazumi ; Shin, Tomoaki

Author_Institution

Comput. & Network Lab., Toshiba Corp., Japan

fYear

1999

fDate

1999

Firstpage

19

Lastpage

22

Abstract

Lateral bipolar transistors using SOI technology (lateral-SOI BJTs) are promising for low-power RF chips in portable communications equipment, owing to their inherently small parasitics. In high-frequency region above 1 GHz, however, the unique device structure degrades the accuracy of the circuit simulation using the MGP model. This paper describes a compact equivalent circuit model for lateral-SOI BJTs, in which parasitic effects depending on the device structure are taken into account precisely, based on results of 3D device simulation

Keywords

SPICE; UHF bipolar transistors; circuit simulation; equivalent circuits; frequency response; microwave bipolar transistors; semiconductor device models; silicon-on-insulator; 1 to 10 GHz; 3D device simulation; RF circuit simulation; SPICE parameter; compact model; equivalent circuit model; frequency response; lateral-SOI BJT; low-power RF chips; model verification; parasitic effects; power gain; Admittance; Analytical models; Capacitors; Carbon capture and storage; Circuit simulation; Equivalent circuits; Fuses; Laboratories; Radio frequency; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1999. SISPAD '99. 1999 International Conference on

Conference_Location

Kyoto

Print_ISBN

4-930813-98-0

Type

conf

DOI

10.1109/SISPAD.1999.799249

Filename

799249