DocumentCode :
3249472
Title :
Programmable parallel processor for video processing
Author :
Nishitani, Takao ; Tamitani, Ichiro ; Harasaki, Hidenobu
Author_Institution :
NEC Corp., Kawasaki, Japan
fYear :
1989
fDate :
0-0 1989
Firstpage :
169
Lastpage :
172
Abstract :
A programmable parallel processor architecture for real-time video signal processing is described. The architecture is composed of several parallel processor clusters and bus-switch units. The bus switch units combine these clusters in a tandem form or in a parallel form. Each parallel processor cluster can execute one frame picture processing in real time. Each element processor in a cluster processes its preassigned subpicture in a frame period. An experimental 36-element processor system using this architecture is developed for picture encoding evaluation. The results indicate that this approach is a promising one in many application areas, including motion picture encoding.<>
Keywords :
computerised picture processing; parallel architectures; bus-switch units; parallel processor architecture; parallel processor clusters; picture encoding evaluation; picture processing; real-time; video signal processing; Image processing; Parallel architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Systems Engineering, 1989., IEEE International Conference on
Conference_Location :
Fairborn, OH, USA
Type :
conf
DOI :
10.1109/ICSYSE.1989.48646
Filename :
48646
Link To Document :
بازگشت