DocumentCode
3249521
Title
Impact of cell layout on the characteristics of 60 V low on-resistance lateral NMOS for power ICs
Author
Plikat, Robert ; Darwish, Mohamed ; Shekar, M.S. ; Williams, Richard K.
Author_Institution
Inst. of Electr. Drives, Bremen Univ., Germany
fYear
1997
fDate
26-29 May 1997
Firstpage
349
Lastpage
352
Abstract
An optimization study has been performed to improve the performance of 60 V power lateral NMOS transistors. It is shown that the 3D effects in closed-cell layout can be utilized to obtain a better trade-off between on-resistance and breakdown voltage. 3D simulations show good agreement with experimental data and are used to gain insight into the device
Keywords
MOS analogue integrated circuits; circuit optimisation; integrated circuit layout; power integrated circuits; 3D simulations; 60 V; breakdown voltage; circuit optimization; closed-cell layout; on-resistance; power ICs; power lateral NMOS transistors; Breakdown voltage; Doping profiles; Leakage current; MOS devices; MOSFETs; Mesh generation; Power electronics; Power integrated circuits; Predictive models; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and IC's, 1997. ISPSD '97., 1997 IEEE International Symposium on
Conference_Location
Weimar
ISSN
1063-6854
Print_ISBN
0-7803-3993-2
Type
conf
DOI
10.1109/ISPSD.1997.601515
Filename
601515
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