The FPGA implementation of dictionary; HW consumption versus latency

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary is in RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.