An efficient and accurate delay library generation with RSM [BiCMOS ASIC process]

In MPU/ASIC design with 0.2 μm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of CKT simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries, 100 times faster without loosing accuracy. In application for a BiCMOS ASIC process, we have verified that the new method has achieved a reduced library creation-time of 1/100 within the delay error of 3%. This technique can be used in our TCAD/DA framework, which gives a predictive TCAD generation of delay-libraries in concurrent ASIC system and process development