DocumentCode
3250180
Title
Practical virtual cell designing environment
Author
Tatsumi, Takaaki ; Nakayama, Hajime ; Mukai, Mikio ; Komatsu, Yasutoshi
Author_Institution
LSI Bus. & Technol. Dev. Group, Sony Corp., Kanagawa, Japan
fYear
1999
fDate
1999
Firstpage
163
Lastpage
166
Abstract
We have developed a novel and practical virtual cell designing environment. For the practical use, the system provides simulators highly calibrated and adaptive to new structure devices and processes; tools for analyzing the effect of process variations on device characteristics or parasite capacitance; and easy-to-use GUI. This environment is used in practical work and has reduced TAT of cell designing to less than one eighth. Furthermore, it has enabled evaluation of even new structured devices
Keywords
electronic design automation; semiconductor device models; semiconductor process modelling; device simulation; graphical user interface; parasitic capacitance; process simulation; turn around time; virtual cell designing environment; Analytical models; Capacitance-voltage characteristics; Circuit simulation; Data mining; Databases; Graphical user interfaces; Integrated circuit interconnections; MOSFETs; Parasitic capacitance; SPICE;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 1999. SISPAD '99. 1999 International Conference on
Conference_Location
Kyoto
Print_ISBN
4-930813-98-0
Type
conf
DOI
10.1109/SISPAD.1999.799286
Filename
799286
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