Interconnect modeling for VLSIs

As scaling is continued down to deep submicron, interconnects become dominating the performance, signal integrity, and reliability of IC chips. However, due to the short history, not much work has been done on the overall interconnect modeling, especially interconnect characterization and statistical interconnect modeling. In interconnect characterization, more systematic methodology should be established in interconnect test structure design and their characterization. New test structures and characterization methods should be developed to characterize the advanced interconnect technology such as low K dielectric and copper. 2D interconnect model library generation has been done by the 2D finite-difference method or finite-element method. However, it takes too long to generate 3D interconnect model library due to the increase of 3D basic structures. Fast multi-pole method or measured equation of inversion are used to speed up the 3D library generation. To avoid errors due to 3D structure partitioning 3D Monte Carlo method is used to simulate the global nets. The ever-increasing clock frequency makes inductive effects more significant. However, it is very challenging to model the on-chip inductance due to its long-range interaction and wide return paths. Worst-case interconnect modeling has been done by the skew-corner method or root-sum-square method. Both methods are too conservative. The newly developed SWIM (Statistically-based Worst-case Interconnect Model generator) improves the worst-case delay within 20%