A design approach for a 6.7-mW 5-GHz CMOS frequency synthesizer using dynamic prescaler

A design approach of 5-GHz CMOS phase locked loop (PLL) based frequency synthesizer is presented in this paper. The power consumption of the synthesizer is minimized using dynamic logic in the frequency divider block consuming 1.89-mW. The operating range of the synthesizer is 4.90 to 5.15-GHz with a total power consumption of 6.7-mW from a single 1.8-V power supply. The synthesizer uses static CMOS inverters in designing the oscillator and buffers. The VCO works from 4.5 to 5.4-GHz with a phase noise of -81.12 dBc/Hz at 600 KHz offset frequency from the carrier for maximum oscillation frequency. The PLL is designed and extracted in TSMC 0.18-mum technology for high frequency reference clock generation in clock distribution networks. In this design, an optimization approach is constructed to maximize the speed and minimize the power and area