A new technique for designing high performance front-end sample and hold circuits

Based on the behavioral modelisation of each element in a sample and hold (S/H) circuit, and using the Verilog-A language, such approach effectively allow us to get the best performances that the circuit can give. Using switched capacitor differential topology, double bootstrapped switches and several native transistors, we optimized with Verilog-A models the amplifier and the switches to end up with the optimized high performance circuit. Post layout simulation of the optimized circuit using CMOS 0.18 μm technology with a V_DD of 1.8 V allowed to reach an SFDR of 88.6 dB for 20 MHz input signal. The circuit was integrated to other building blocks to construct a pipelined ADC which is now under fabrication.