Voltage and sizing optimization for low power buffered digital designs

Author

Farbiz, F. ; Behnam, A. ; Emadi, M. ; Esfandiarpoor, B. ; Kusha, A. Afzali

Author_Institution

Dept. of ECE, Tehran Univ., Iran

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

20

Lastpage

23

Abstract

A circuit design style with separate logic and buffer stages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much more accurate than the ones proposed in the previous works.

Keywords

SPICE; VLSI; buffer circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; integrated logic circuits; logic design; low-power electronics; SPICE simulation; VLSI; energy delay product; figure of merit; integrated logic circuits; logic design; low power buffered digital design; supply voltage; transistor sizing optimization; voltage optimization method; Capacitance; Circuit simulation; Delay; Design optimization; Digital circuits; Equations; Logic circuits; Logic design; Logic devices; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434195

Filename

1434195