Finite state machine realization of IIR digital filters

A method is proposed for representing an infinite impulse response (IIR) digital filter as a finite-state machine (FSM). This representation has a maximum error of only 1/2 bit from the final result of infinite accuracy arithmetic and has no increase in errors during the processing period. The realization avoids the effects of coefficient quantization and multiplication arithmetic errors caused by finite word length on the performance of a digital signal processing (DSP) system. A graph theory method is presented for removing the oscillations from the system with a minimal increase in noise and without any increase in system complexity.<>