The DF-dice storage element for immunity to soft errors

This paper describes the delay filtered dual interlocked storage cell, which is immune to single event transients on any of the inputs and single event upsets within the storage cell. The increase in area and speed of an application specific integrated circuit (ASIC) employing the proposed cells are proportional to the targeted single-event transient (SET) pulse-width. A standard ASIC can easily be converted to a soft-error tolerant design by simply replacing all the storage elements with the proposed cells. The area and speed performance of the proposed cells targeted for an 800ps wide SET have been evaluated. The resulting designs are immune to soft-errors with acceptable area penalty and modest degradation in speed.