Title :
High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme
Author :
Tsuji, K. ; Takeuchi, K. ; Mogami, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC, Sagamihara, Japan
Abstract :
It is demonstrated that low temperature activation of the source/drain impurities, induced by the re-crystallization of an amorphous substrate layer, is effective for realization of scaled CMOS with abrupt junction profiles. Physical 50 nm gate length pFETs with high drive current and good short channel behaviour were obtained.
Keywords :
CMOS integrated circuits; MOSFET; doping profiles; electric current; impurity distribution; recrystallisation; semiconductor device manufacture; semiconductor device testing; abrupt junction profiles; amorphous substrate layer; drive current; gate length; low temperature activation; pFETs; pMOSFETs; physical gate length; re-crystallization; scaled CMOS; short channel behaviour; source/drain impurities; Amorphous materials; Annealing; CMOS process; Degradation; Impurities; MOSFETs; National electric code; Silicon; Temperature; Thin film transistors;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799314
