Author :
Diaz, Carlos H. ; Young, K.L. ; Hsu, J.H. ; Lin, J.C.H. ; Hou, C.S. ; Lin, C.T. ; Liaw, J.J. ; Wu, C.C. ; Su, C.W. ; Wang, C.H. ; Ting, J.K. ; Yang, S.S. ; Lee, K.Y. ; Wu, S.Y. ; Tsai, C.C. ; Tao, H.J. ; Jang, S.M. ; Shue, S.L. ; Hsieh, H.C. ; Wang, Y.Y.
Abstract :
This paper describes a leading-edge 0.18 /spl mu/m CMOS logic foundry technology. Very aggressive design rules and borderless contacts render a 4.4 /spl mu/m/sup 2/ embedded (synchronous cache) 6T SRAM cell demonstrated in a 1 Mb vehicle with very high yield. Robust dual-gate oxides were developed to support 1.5-2 V core logic as well as 3.3 V periphery (I/O) circuitry. Advanced modular core device technology using 32 /spl Aring/ oxides for 1.8-2 V operation and 27 /spl Aring/ oxides for 1.5-1.7 V applications support competitive high-performance (MPU/graphics) or low-standby power (mobile) applications. Transient-enhanced diffusion is effectively used in I/O devices to enhance hot-carrier lifetime. This is the first 0.18 /spl mu/m technology demonstrating a highly manufacturable 6 to 7 level low-k (HSQ)/AlCu interconnect system with tightest metal pitch (0.46 /spl mu/m M1 and 0.56 /spl mu/m at intermediate levels), as well as aggressive borderless and fully stacked vias without poisoning problems. AlCu/FSG and dual-damascene Cu/oxide interconnect options have also been proven with comparable SRAM yield to the AlCu/HSQ system.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; dielectric thin films; electrical contacts; hot carriers; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; low-power electronics; permittivity; 0.18 micron; 0.46 micron; 0.56 micron; 1 Mbit; 1.5 to 1.7 V; 1.5 to 2 V; 1.8 to 2 V; 27 angstrom; 3.3 V; 32 angstrom; AlCu; AlCu/FSG interconnects; AlCu/HSQ system; CMOS logic foundry technology; CMOS logic technology; Cu-SiO/sub 2/; I/O devices; IC yield; MPU applications; SRAM yield; borderless contacts; core logic; design rules; dual gate oxide; dual-damascene Cu/oxide interconnects; dual-gate oxides; embedded synchronous cache 6T SRAM cell; graphics applications; high-performance applications; hot-carrier lifetime; low-k HSQ/AlCu interconnect system; low-k interconnect; low-power applications; low-standby power mobile applications; manufacturability; metal pitch; modular core device technology; periphery I/O circuitry; stacked vias; transient-enhanced diffusion; via poisoning; CMOS logic circuits; CMOS technology; Foundries; Integrated circuit interconnections; Lead; Logic circuits; Logic devices; Random access memory; Robustness; Vehicles;
