Time partitioning framework for partially reconfigurable systems

The FPGAs architectures allow the overlap between execution and reconfiguration. Indeed, fractions of the application can be configured at the same time that others fractions of the application can be executed. This approach is called partially reconfiguration that used for partially reconfigurable FPGAs. The partially reconfiguration approach can be used to fit a large application into the FPGA device by partitioning the application over time. At each partition, set of tasks are configured and other sets of tasks are executed. This partitioning over time of execution and configuration of tasks is achieved so that the latency of the application is optimal. In this paper, we introduce a time partitioning and a design flow approach for partially reconfigurable systems.