Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SADD) process for 0.15 /spl mu/m stand-alone and embedded DRAMs

A novel integration technology with capacitor over metal (COM) for 0.15 /spl mu/m stand-alone and embedded DRAMs is developed using a self-aligned dual damascene (SADD) process, which offers great breakthroughs. First, many back-end metallization issues encountered in conventional COB (capacitor over bit line) DRAMs are simply overcome because the capacitor is formed after the metal lines. Secondly, memory cell capacitors can be integrated much more simply and easily compared to those of conventional COB technology because the memory cell contact and storage node are formed simultaneously. Furthermore, transistor performance can be greatly improved because a novel poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor is integrated at temperatures below 400/spl deg/C.