A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

Author

Ajmera, A. ; Sleight, J.W. ; Assaderaghi, F. ; Bolam, R. ; Bryant, A. ; Coffey, M. ; Hovel, H. ; Lasky, J. ; Leobandung, E. ; Rausch, W. ; Sadana, D. ; Schepis, D. ; Wagner, L.F. ; Wu, K. ; Davari, B. ; Shahidi, G.

Author_Institution

IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

15

Lastpage

16

Abstract

A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low V/sub T/ device, ESD diode, and decoupling capacitance). This technology was applied to a 64 b RISC processor.

Keywords

CMOS digital integrated circuits; copper; electrostatic discharge; integrated circuit interconnections; integrated circuit metallisation; lithography; microprocessor chips; protection; reduced instruction set computing; semiconductor diodes; silicon-on-insulator; 0.22 micron; 64 bit; CMOS on SOI technology; CMOS-SOI technology; Cu; Cu BEOL; ESD diode; RISC processor; Si-SiO/sub 2/; bulk technology; chip level performance; circuit elements; decoupling capacitance; device elements; gate lithography; low threshold voltage device; metallization; nonfully depleted device; CMOS technology; Circuits; Delay; Doping; Heating; Isolation technology; Space technology; Stereolithography; Substrates; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799317

Filename

799317