A low voltage erase technique for DINOR flash memory devices

Author

Zhizheng Liu ; Ma, T.P.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

17

Lastpage

18

Abstract

A novel low voltage (/spl les/5 V) erase scheme for DINOR (divided bit line NOR) flash memory devices, designated pulse agitated substrate hot electron injection (PASHEI), is demonstrated. No extra process or cell structure modification is needed. In fact, unlike the conventional DINOR structure, no triple well is necessary, and sector erase can be easily implemented. Excellent endurance performance has been obtained. These results suggest that PASHEI is an excellent candidate for future scaled flash technology.

Keywords

NOR circuits; flash memories; hot carriers; integrated circuit reliability; integrated memory circuits; 5 V; DINOR flash memory devices; DINOR structure; PASHEI LV erase technique; divided bit line NOR flash memory devices; endurance performance; low voltage erase technique; pulse agitated substrate hot electron injection erase scheme; scaled flash technology; sector erase; Electron emission; Flash memory; Low voltage; MOSFETs; Manufacturing; Nonvolatile memory; Substrate hot electron injection; Timing; Tunneling; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799318

Filename

799318