Title :
0.18 /spl mu/m metal gate fully-depleted SOI MOSFETs for advanced CMOS applications
Author :
Chen, J. ; Maiti, B. ; Connelly, D. ; Mendicino, M. ; Huang, F. ; Adetutu, O. ; Yu, Y. ; Weddington, D. ; Wu, W. ; Candelaria, J. ; Dow, D. ; Tobin, P. ; Mogab, J.
Author_Institution :
Networking & Comput. Syst. Group, Motorola Inc., Austin, TX, USA
Abstract :
We report here for the first time a 0.18 /spl mu/m fully-depleted SOI process with PVD TiN metal gate. As midgap work function metal gate and very light channel doping were used, threshold voltage can be easily controlled in /spl plusmn/300 mV to /spl plusmn/500 mV range and on-wafer V/sub t/ variation was only about /spl plusmn/5 mV. Short channel effects can be further improved when silicon film thickness is thinner than 300 /spl Aring/. Subthreshold slope was kept below 75 mV/dec even for subnominal devices and V/sub t/ roll-offs for both N- and P-MOSFETs were very small.
Keywords :
CMOS integrated circuits; MOSFET; doping profiles; semiconductor device measurement; semiconductor device metallisation; silicon-on-insulator; sputtered coatings; titanium compounds; work function; 0.18 micron; 300 angstrom; 300 to 500 mV; CMOS applications; N-MOSFETs; P-MOSFETs; PVD TiN metal gate; Si-SiO/sub 2/; TiN; channel doping; fully-depleted SOI process; metal gate fully-depleted SOI MOSFETs; midgap work function metal gate; on-wafer threshold voltage variation; short channel effects; silicon film thickness; subthreshold slope; threshold voltage; Atherosclerosis; CMOS process; Delay; Doping; Lighting control; MOSFETs; Semiconductor films; Silicon; Threshold voltage; Tin;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799322
