A parallel pipeline ADC with a Sub-ADC employing an improvized dynamic comparator

This paper presents an analog to digital converter (ADC) capable of resolving 8 bits at a sampling rate of 250 MSPS. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated charge injection error in order to maintain good overall accuracy. Simulation showed non-linearity figures of -0.3173LSB ¿ DNL ¿ 0.28LSB and -0.0373LSB ¿ INL ¿ 0.7LSB. From the sinusoid response, SNDR turns out to be 49.6 dB which yields an ENOB of 7.94 bits. Power consumed by the ADC at the highest sampling rate of 250 MSPS is ¿ 108 mW using a power supply of 1.8 V. The ADC occupies an area of 2.371 mm².