High performance fully and partially depleted poly-Si surrounding gate transistors

High performance poly-Si surrounding gate transistors have been demonstrated. A mobility of 567 cm/sup 2//V-s and a high I/sub on//I/sub off/ ratio of 1.6/spl times/10/sup 9/ were achieved. To our knowledge, this is the best performance reported to date in TFT devices. By controlling the channel doping and gate oxide thickness, partially depleted (PD) and fully depleted (FD) transistors were fabricated. An analytic solution of the electric potential inside the FD transistor channel has been used to understand device performance. Finally, we demonstrate good uniformity of the subthreshold characteristics in this 3D transistor structure.