High-level fault simulation methodology for QDI template-based asynchronous circuits

Complexity of design and the lack of suitable test methodology are the major obstacles for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuits is accepted as an effective way to decrease the complexity of design. However, test frameworks such as fault simulator for synchronous circuits are not applicable for template based asynchronous circuits. In this paper we study transistor-level single stuck-at faults in traditional asynchronous templates and categorize their effects on the functionality of circuit. We prove by a mathematical specification that single stack-at fault in Pre-Charge Full Buffer templates has one of the three effects: deadlock, token generation and token dropping. This categorization is used to introducing a new high level fault simulation methodology for these circuits. Based on this strategy we develop a fault simulator and experimental results show the effectiveness of the proposed fault simulation methodology.