DocumentCode :
3251134
Title :
Fabrication and electrical performance of high aspect ratio gated silicon field emission arrays
Author :
Temple, D. ; Gray, H.F. ; Ball, C.A. ; Mancusi, J.E. ; Palmer, W.D. ; McGuire, G.E. ; Shaw, J.L.
Author_Institution :
Electron. Technol. Div., MCNC, Research Triangle Park, NC, USA
fYear :
1995
fDate :
July 30 1995-Aug. 3 1995
Firstpage :
113
Lastpage :
117
Abstract :
This paper describes a new fabrication approach for field emitter arrays that uncouples the emitter or column height from the gate aperture. In this approach, low pressure chemical vapor deposition (LPCVD) of SiO/sub 2/, which deposits conformally on the tip-on-post structure, is employed followed by a series of photoresist planarization layers and side wall SiO/sub 2/ etch procedures to create small apertures. This procedure is fundamentally different from previous planarization and etch-back techniques.
Keywords :
CVD coatings; conformal coatings; etching; semiconductor technology; silicon; silicon compounds; vacuum microelectronics; Si; SiO/sub 2/; aspect ratio; conformal coating; electrical performance; fabrication; gate aperture; low pressure chemical vapor deposition; photoresist planarization; side wall etching; silicon field emission array; tip-on-post structure; Apertures; Capacitance; Chemical vapor deposition; Etching; Fabrication; Insulation; Planarization; Resists; Silicon; Transconductance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Vacuum Microelectronics Conference, 1995. IVMC., 1995 International
Conference_Location :
Portland, OR, USA
Print_ISBN :
0-7803-2143-X
Type :
conf
DOI :
10.1109/IVMC.1995.487004
Filename :
487004
Link To Document :
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