Design and implementation of novel multi-layer mixed-signal on-chip neural networks

New feed-forward neural network architectures are proposed for general purpose mixed-signal neural networks. By using time-multiplexing in the networks, high number of neurons and synapses can be integrated on the chip and the number of required interconnections is reduced. For training, perturbative training (Madaline Rule III) is applied, which is more robust for implementing mixed-signal designs. Training the network with node perturbation is faster, however, implementing node perturbation adds to the network complexity. In the proposed design most of the limiting factors of this training rule are solved by performing the operations in current mode and using counters. Arrays of mixed-signal multiplying-digital-to-analog-converters (MDAC) blocks are used for synaptic multiplication. A compact architecture with a more linear transfer function is used for the MDAC to reduce the area, power consumption and noise. The proposed network is implemented using TSMC CMOS 0.18mum technology