Title :
Improvement of CoSi/sub 2/ stability on fine grain sized poly-Si using nitrogen implantation through Co monosilicide and its effect on 0.18 /spl mu/m dual gate CMOS
Author :
Jong-Uk Bae ; Dong Kyun Sohn ; Ji-Soo Park ; Byung Hak Lee ; Chang Hee Han ; Jae Jeong Kim
Author_Institution :
R&D Div., LG Semicon. Co. Ltd., Cheongju-si, South Korea
Abstract :
CoSi/sub 2/ has been studied for sub-quarter micron high speed CMOS logic devices, because of low sheet resistance on fine patterned poly-Si lines. For sub-quarter micron CMOS, dual gate is a key technology to realize high performance MOS devices. Recently, dual gate technology has been proposed using simultaneous gate and source/drain doping. In this case, small grain sized poly-Si is necessary to enhance diffusion and minimize gate depletion. However, the thermal stability of CoSi/sub 2/ on fine grain sized poly-Si has not been studied. Nitrogen implantation followed by Co deposition was investigated (Kuroi et al., 1993), but it was difficult to form CoSi/sub 2/ of low resistance, since cobalt to silicon reaction was greatly retarded by nitrogen atoms. In this paper, we found that nitrogen implantation through a Co monosilicide layer improved thermal stability up to 1000/spl deg/C for 30 s, without increase of sheet resistance in a small geometry. Furthermore, the implanted nitrogen also enhanced gate oxide reliability with high performance 0.18 /spl mu/m CMOS dual gate devices fabricated using simultaneous gate and source/drain doping.
Keywords :
CMOS logic circuits; cobalt compounds; doping profiles; electric resistance; grain size; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; ion implantation; nitrogen; thermal stability; 0.18 micron; 1000 C; 30 s; CMOS dual gate devices; CMOS dual gate technology; CMOS logic devices; Co deposition; Co monosilicide; Co monosilicide layer; CoSi; CoSi/sub 2/ stability; CoSi/sub 2/-Si:N; MOS devices; SiO/sub 2/-Si; cobalt to silicon reaction; diffusion; dual gate CMOS; fine grain sized poly-Si; fine patterned poly-Si line; gate depletion; gate oxide reliability; grain size; low resistance CoSi/sub 2/ formation; nitrogen implantation; sheet resistance; simultaneous gate/source/drain doping; thermal stability; Atomic layer deposition; CMOS technology; Cobalt; Doping; Logic devices; MOS devices; Nitrogen; Silicon; Thermal resistance; Thermal stability;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799336