A low power 700MSPS 4bit time interleaved SAR ADC in 0.18um CMOS

The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using Gilbert cell preamplifier in one of comparator detectors. It reduces the power consumption by approximately 33%. The ADC is implemented in 0.18¿m CMOS technology and has total power consumption of 23.3mw at sampling frequency of 700MSPS for an input swing of 1V peak to peak. The proposed SAR ADC gives SNDR of 23.9dB, SFDR of 32.6dB and THD of -37.8dB at Nyquist rate. The proposed ADC enables a larger input swing with figure of merit of 2.5 which is higher than that of SAR ADCs reported in the literature.