Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS

Author

Baohong Cheng ; Inani, A. ; Rao, R. ; Woo, J.C.S.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

69

Lastpage

70

Abstract

The effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher I/sub dsat/ and g/sub msat/, lower I/sub off/, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at V/sub DD/=0.6 V is equivalent to that of a conventional device operated at V/sub DD/=1.5 V.

Keywords

CMOS integrated circuits; MOSFET; doping profiles; electric current; high-speed integrated circuits; semiconductor device measurement; 0.6 V; 1 V; 1.5 V; LAC device; MOSFETs; channel engineering; device performance; device switching speed; double-halo MOSFETs; drain saturation current; high speed CMOS; lateral asymmetric channel MOSFETs; off current; power supply; saturation transconductance; short-channel performance; velocity overshoot effects; DH-HEMTs; Doping; Electrons; Energy consumption; Implants; Los Angeles Council; MOS devices; MOSFETs; Power engineering and energy; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799344

Filename

799344