DocumentCode
3251430
Title
ESD protection circuit with an improved ESD capability for input or output circuit protection
Author
Jung, Min Chul ; Hawng, Sang Joon ; Sung, Man Young ; Kang, Ey Goo
Author_Institution
Dept. Electr. Eng., Korea Univ., Seoul, South Korea
fYear
2005
fDate
7-10 Aug. 2005
Firstpage
468
Abstract
An ESD protection circuit in chip level protection is proposed as the electrostatic discharge (ESD) clamping circuit such as thick field oxide (TFO), grounded gate MOS (GGNMOS) and separated stages for input or output protection. The ESD protection circuits for input pad and output pad were implemented from the proposed ESD protection circuit. The realized protection circuits for input pad and output pad have been simulated by HSPICE and approved the improved ESD capability.
Keywords
MOS integrated circuits; electrostatic discharge; ESD capability; ESD clamping circuit; ESD protection circuit; HSPICE; chip level protection; circuit protection; electrostatic discharge; grounded gate MOS; thick field oxide; Circuit simulation; Clamps; Dielectrics and electrical insulation; Electric breakdown; Electrons; Electrostatic discharge; Manufacturing processes; Protection; System-on-a-chip; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. 48th Midwest Symposium on
Print_ISBN
0-7803-9197-7
Type
conf
DOI
10.1109/MWSCAS.2005.1594139
Filename
1594139
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