DocumentCode
3251437
Title
The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling
Author
Kimizuka, N. ; Yamamoto, T. ; Mogami, T. ; Yamaguchi, K. ; Imai, K. ; Horiuchi, T.
Author_Institution
ULSI Device Dev. Labs., NEC Corp., Sagamihara, Japan
fYear
1999
fDate
14-16 June 1999
Firstpage
73
Lastpage
74
Abstract
This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.
Keywords
CMOS integrated circuits; MOSFET; dielectric thin films; hot carriers; semiconductor device reliability; semiconductor device testing; thermal stability; tunnelling; CMOS devices; MOSFET scaling; NMOSFET; PMOSFET; Si; SiO/sub 2/-Si; bias temperature instability; bias-temperature instability; degradation mechanism; device degradation; device lifetime; direct-tunneling electron transport; direct-tunneling hole transport; direct-tunneling ultra-thin gate oxide; hot-carrier degradation; hot-carrier induced degradation; reliability scaling; stress voltage dependence; supply voltage; threshold voltage; Degradation; Hot carrier injection; Hot carriers; Leakage current; MOSFET circuits; Nitrogen; Silicon; Stress; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-93-X
Type
conf
DOI
10.1109/VLSIT.1999.799346
Filename
799346
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